The invention relates to a method of generating estimates of valid input signal values at sampling instants. The invention further relates to apparatus for generating estimates of valid input signal values at sampling instants. The invention still further relates to a Viterbi decoder utilising such a method or including such apparatus.
There is a continuing and increasing desire for larger data capacity on optical discs. Additionally, there is a desire for greater speed in reading the data from the disc. These two demands arise from the increasing use of optical storage media in video and high speed data applications and both these applications require performance far greater than that achieved in the original audio compact disc applications. As a result there is a demand for methodologies which allow for recovery of the data at rates which are at or near the limit achievable given the physics of the media, mechanics, optics, and electronics.
One of the consequences is an increasing level of inter-symbol interference in the data channel when reading data from the disc. The use of Viterbi decoders in reading data from optical discs has been disclosed in U.S. Pat. Nos. 5,661,709 and 5,450,389. These documents disclose arrangements in which the input signal is digitised in an A/D converter and all the manipulations are carried out in the digital domain. DVD systems currently being designed have the capability of decoding data at sixteen times nominal speed which represents a channel bit rate in excess of 400 Mb/s. As a result it requires very high speed digital signal processing leading to increased costs.
It is an object of the invention to enable the provision of a decoder, particularly, but not exclusively, for data read at high speed from an optical disc without requiring the use of high speed digital signal processors.
The invention provides a method of generating estimates of valid input signal values at sampling instants comprising the steps of;
a) receiving an input signal,
a) slicing the input signal at successive sampling instants at a given slicing level,
c) detecting in the sliced signal a given data sequence,
d) slicing the input signal at successive sampling instants at an estimated signal value adapted to one data bit of the given data sequence,
e) storing the result of step d) so that it is available when step c) has been completed, and
f) causing the estimated value to increase or decrease in dependence on whether the stored result indicates the input signal was above or below the estimated value when the one data bit of the given sequence occurred.
A necessary part of a Viterbi decoder is a means for deriving estimates of the valid values that the signal may have at the sampling instants. The method described in the preceding paragraph enables estimated values to be generated when a given sequence of bits is detected even though the bit value of interest has been replaced by succeeding bits by the time the given sequence has been received and detected. It has the advantage of not requiring the storage of the actual received value, which due to the channel bandwidth will be an analogue value. Instead of storing the received sampled value at the time the bit of interest was received an indication of whether the value was above or below the estimated value is stored. When the given sequence is detected this stored indication is used to update the estimated value by increasing or decreasing it by a predetermined increment. The estimated value will, as a result, converge to the correct value over a number of received data sequences.
In an optical disc player such as a DVD player, the physical aperture of the optical system is such that one bit period is much shorter than the total response of the photodiode system so inter-symbol interference occurs. In present laser optic recording there is a minimum number of consecutive xe2x80x9c1sxe2x80x9d or xe2x80x9c0sxe2x80x9d that are allowed in the data encoding (d-constraint). This number is currently three, that is in any data sequence must contain a minimum of three consecutive xe2x80x9c1sxe2x80x9d or three consecutive xe2x80x9c0sxe2x80x9d. This leads to a signal waveform that appears to be band limited but whose peak and trough levels are functions of the number of bits of the same value. The peak achieved with only three successive xe2x80x9c1sxe2x80x9d will be lower than if there are many successive xe2x80x9c1sxe2x80x9d (up to seventeen are allowed in the DVD standard). The sequences where only three successive bits have the same value, that is 01110 and 10001, are known as I3 states.
The method may involve in step c) two inverse data sequences being detected, in step d) the input signal being further sliced at a second estimated level adapted to a corresponding bit of the inverse sequence, in step e) both results being stored, and in step f) the respective estimated value being increased or decreased when the given or inverse sequence is detected.
The input signal may be derived from an optical read head and the given sequence may be 01110.
By using this method the xe2x80x9cI3xe2x80x9d states, that is the sequences 01110 and 10001, may be detected and used to update the estimated valid values when decoding data read from an optical disc.
The invention further provides apparatus for generating estimates of valid input signal values at sampling instants comprising an input for receiving an input signal, a first data slicer for slicing the input signal at a given slicing level, a detector for detecting a given data sequence in the sliced signal, a second data slicer for slicing the input signal at a signal value estimated for a given data bit of the given data sequence, a memory element for storing the output of the second data slicer when slicing the given data bit, and incrementing means for increasing the estimated value when the stored output of the second data slicer indicates that the input signal value was above the estimated value when the given data bit was sliced and for reducing the estimated value when the stored output of the second data slicer indicates that the input signal value was below the estimated value when the given data bit was sliced.
The apparatus may further comprise a second detector for detecting the inverse of the given data sequence, a third data slicer for slicing the input signal at a signal value estimated for a given data bit of the inverse of the given data sequence, a second memory element for storing the output of the third data slicer when slicing the given data bit of the inverse of the given data sequence, and second incrementing means for increasing the estimated value when the stored output of the third data slicer indicates that the input signal value was above the estimated value when the given data bit of the inverse of the given data sequence was sliced and for reducing the estimated value when the stored output of third data slicer indicates that the input signal value was below the estimated value when the given data bit of the inverse of the given data sequence was sliced.
The detector may comprise a shift register having a serial input to which the output of the first data slicer is connected and a logic decoder having inputs connected to parallel outputs of the shift register, said logic decoder giving an output indicating the presence of the given data sequence in the shift register.
This enables a given sequence having a length equal to the number of stages of the shift register and number of inputs of the logic decoder to be detected. The particular sequence detected will depend on the construction of the logic decoder and the selection of the outputs of the shift register applied to the inputs of the logic decoder.
The memory element may comprise a further shift register having a serial input to which the output of the second data slicer is connected and a serial output connected to said incrementing means to determine whether it increments or decrements, said incrementing means being stepped by the output of the logic decoder.
The result of slicing the input signal at the centre bit of the given sequence can thereby be accessed after the given sequence has been detected. It will be apparent that this sequence cannot be detected until some time after the receipt of the centre bit of the sequence as further bits have to be received before the sequence is complete.
The first and second detectors may each comprise a shift register having a serial input to which the output of the first data slicer is connected and a logic decoder having inputs connected to parallel outputs of the shift register, said logic decoders giving outputs indicating the presence of the given or inverse data sequence in the shift register.
This enables both the given sequence and the inverse of the given sequence to be detected.
The first and second memory elements may each comprise a further shift register having a serial input to which respective outputs of the second and third data slicers are connected and a serial output connected to respective incrementing means, said incrementing means being enabled by the output of the respective logic decoder.
The first or each of first and second incrementing means may comprise an up/down counter which is clocked by the output of the respective detector and whose count direction is determined by the state of the respective memory element and a digital to analogue converter (DAC) whose output determines the estimated signal value.
This enables an analogue value to be increased or decreased in steps equal to the least significant bit of the DAC. In this way the estimated value can converge towards the correct value.
The outputs of the DACs may be applied to either end of a tapped resistor chain, wherein the first and second estimated values are derived from tapping points on the resistor chain.
The resistor chain may also provide tapping points from which estimated valid values for other data sequences having the same length as the given sequence may be derived.
The invention further provides a Viterbi decoder including such an arrangement for generating estimates of valid input signal values at sampling instants or using such a method for generating estimates of valid input signal values at sampling instants.